Modern integrated circuits are constructed with up to several million active devices, such as transistors and capacitors, formed in and on a semiconductor substrate. Interconnections between the active devices are created by providing a plurality of conductive interconnection layers, such as polycrystalline silicon and metal, which are etched to form conductors for carrying signals. The conductive layers and interlayer dielectrics are deposited on the silicon substrate wafer in succession, with each layer being, for example, on the order of 1 micron in thickness.
A gate structure is an element of a transistor. FIG. 1 illustrates an example of a gate stack 8. A semiconductor substrate 10 supports a gate insulating layer 16, which overlaps doped regions (source/drain regions) in the substrate (12 and 14), and the gate insulating layer supports a gate 18, which is typically polycrystalline silicon. On the gate is a metallic layer 30. The metallic layer may be separated from the gate by one or more other layers, such as nitrides, oxides, or silicides, illustrated collectively as barrier layer 20. The metallic layer may in turn support one or more other layers (collectively 40), such as nitrides, oxides, or silicides. Oxide 22 may be formed on the sides of the gate to protect the gate oxide at the foot of the gate stack; and insulating spacers 24 may be formed on either side of the gate stack. Furthermore, contacts to the source/drain regions in the substrate, and to the gate structure, may be formed.
The continuous scaling of VLSI technologies has demanded a gate dielectric that is scaled down in thickness while maintaining the required leakage performance. Silicon dioxide met these requirements down to a thickness of about 25 Angstroms. Below this thickness it first becomes marginal for leakage; then the thickness control itself and finally the problem of boron penetration from the polysilicon on the gate oxide into the substrate becomes a very critical issue as the technologies moves to P+ poly gate for PMOSFETs for better performance. Nitrided SiO2, in which nitrogen is incorporated (2 to 3%) by annealing the gate oxide in N2O or NO, has been proposed. This dielectric is robust for boron penetration, due to the fact that nitrided SiO2 is better for leakage because of the slightly higher dielectric constant. This dielectric can be scaled down to about 22 to 24 Angstroms (physical thickness), below which it fails due to leakage and boron penetration. Since NO annealing also increases the oxide thickness, there is a limit to the amount of nitrogen that can be incorporated for a required thickness. For technology that uses a CD (critical dimension, which corresponds to the width of the gate) of 70 nm and smaller, the gate dielectric thickness should be in the range 14 to 16 Angstroms EOT (equivalent oxide thickness) which cannot be met by nitrided SiO2. A new material is needed to meet all the requirements.
Current technology uses nitrided SiO2 which is formed by first growing SiO2 by dry or wet oxidation and the oxide is typically annealed in NO, at about 850° C. to 900° C. for at least 15 minutes, to incorporate sufficient nitrogen. It is very difficult to scale the thickness below about 18 Angstroms, since the oxidation is too fast and annealing in NO grows significant amounts of oxide. The dielectric is also physically too thin for an EOT of 15 to 16 Angstroms. At this thickness, there is too much tunneling current through the dielectric, resulting in high leakage. The thin dielectric also gives rise to unacceptable boron penetration. Incorporating more nitrogen calls for an increased anneal which would increase the oxide thickness beyond the required limit.